Referring to FIG. 9, the background technology will be explained.
One of lateral type power transistors used for power sources such as a low drop-out power source is a power transistor having a base layer on an upper part of a semiconductor substrate, a plurality of emitter regions provided separately from each other on an upper part in the base layer, and a collector region provided apart from the emitter region by a predetermined distance so as to surround them, the plurality of emitter regions being connected together in parallel to be used. The power transistor mentioned above is configured as follows.
In FIG. 9, the power transistor 1 has an N+ buried layer formed on a predetermined portion of an upper part of a substantially rectangular P− type semiconductor substrate 2, an N− type base layer 4 formed by vapor phase epitaxy so as to cover the buried layer 3, and a P− isolation region 5 formed on the peripheral part of the base layer 4 by thermal diffusion. The part within the P− isolation region of the base layer 4 is partitioned in three compartments 9a, 9b, and 9c by dividing the inside part in three by means of a guard ring 8 comprised of an N++ region 6 and an N+ region provided on the upper part of the base layer 4, along approximately the periphery of the substrate in parallel with the side of the rectangular outline of the semiconductor substrate 2.
A plurality of emitter regions 12 having a square pattern of a P++ region 10 and a P+ region 11 with a predetermined depth respectively are arranged one by one at a predetermined first pitch in the horizontal direction of the substrate surface and at a predetermined second pitch in the perpendicular direction thereof, on the upper part inside the base layer 4 in each compartment 9a, 9b, or 9c. Furthermore, the upper part of the base region 4 is provided with a P+ collector region 13 in such a manner as to surround each emitter region 12 spaced by a predetermined space, so that a PNP transistor 14 is formed locally with being centered at each emitter region 12.
An insulating layer of such as SiO2 is formed on the base layer 4, the emitter region 12, the collector region 13, etc. A square emitter contact 16 smaller than the emitter region 12 is formed on a part of the insulating layer over the emitter region 12 so as to conduct the emitter region 12. On the other hand, a rectangular collector contact 17 is formed on a part of the insulating layer over the collector region 13 between the emitter regions 12 adjacent to each other in the longitudinal direction along the arranged direction of the emitter regions 12, so as to conduct the collector region 13. Moreover, a base contact 18 is formed on a predetermined part of the periphery of the semiconductor substrate 2.
An emitter wiring patterned to connect in parallel each emitter region 12 through each emitter contact 16 and a collector wiring 20 patterned to connect in parallel each collector region 13 through each collector contact 17 is formed on the insulating layer. Reference numbers 22 and 23 designate a collector pad and an emitter pad respectively provided on the insulating layer 15.
However, because the rectangular collector contact 17 in the conventional technology is provided in the direction of the arrangement of the emitter regions 12 between two emitter regions 12 adjacent to each other in the longitudinal direction, the distance between the PNP transistor units 14 centered at each emitter unit 12 cannot be decreased. That is, the above fact causes difficult situation to make the power transistor 1 be more miniaturized.
In addition, the collector contact 17 is formed adjacent to each emitter contact 16 in the longitudinal direction, so that the electric current when the transistor is operated concentrates on a part where the collector contact 17 is nearest to each emitter contact 16. Therefore, the electric current does not flow effectively to the collector region 13, and this leads to a low electric current efficiency.
Additionally, because the base contact 18 is located on a predetermined part of the periphery of the semiconductor substrate 2 and the guard ring 8 is provided so as to divide the inside of the semiconductor substrate 2 in parallel with the side of the rectangular outline into three compartments, the base resistance component of the PNP transistor unit 14 becomes large as the transistor unit gets close to the central part inside the divided three compartments 9a, 9b, and 9c. In consequence, the PNP transistor 14 becomes difficult to be operated and especially the current gain at the large current region becomes deteriorated. Though it is therefore necessary that number of the PNP transistor units should be increased to improve the characteristics, this matter is contrary to miniaturizing the power transistor 1.